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NXP Semiconductors /MIMXRT1011 /LPI2C1 /MCCR0

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Interpret as MCCR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKLO0CLKHI0SETHOLD0DATAVD

Description

Master Clock Configuration Register 0

Fields

CLKLO

Clock Low Period
CLKHI

Clock High Period
SETHOLD

Setup Hold Delay
DATAVD

Data Valid Delay

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data